Myril B. Reed Best Paper Award Winners
The Myril B. Reed Best Paper Award was established in 1977 in connection with the 20th Midwest Symposium on Circuits and Systems, held at Texas Tech University. Oral tradition holds that the award was established by Professor Richard Saeks, one of the organizers of the 1977 symposium, who had been a student of Myril B. Reed at Colorado State University. Saeks named the award in honor of Professor Reed, one of the founders of the Midwest Symposium.
This account is based in part on recollections of the early history of MWSCAS and in part on documented evidence of the academic relationship between Saeks and Reed. However, surviving archival records that explicitly document the establishment of the award have not yet been located.
| No. | Year Paper Presented | Year Awarded Announced | Author(s) | Title |
|---|---|---|---|---|
| 20th | 1977 | 1978 | W. Kenneth Jenkins | Techniques for High-Precision Digital Filtering with Multiple Microprocessors |
| 21st | 1978 | 1979 | Sung Mo Kang | An Efficient Design of Large-Scale Communication Networks with a Decomposition Technique |
| 22nd | 1979 | 1980 | No winner selected | |
| 23rd | 1980 | 1981 | Clement F. Lee and W. Kenneth Jenkins | Switched-capacitor circuit analysis based on modified nodal analysis |
| 24th | 1981 | 1982 | R. L. Geiger and P. E. Allen | Switched Resistor Filters |
| 25th | 1982 | 1983 | Ann Miller Millman | An Application of Computer Graphics to Combat Vehicle Design |
| 26th | 1983 | 1984 | Byeong G. Lee and Alan Willson | All Two-Transistor Circuits Possess at Most Three DC Equilibrium Points |
| C.S. Gargour, B. Nowrouzian and V. Ramachandran | Design Biquadratic Stray Insensitive Switched Capacitor Filters Using Unit Delays and Finite Gain Amplifiers as Basic Building Blocks | |||
| 27th | 1984 | 1985 | M. Odyniec and L. O. Chua | Synchronization in Nonlinear Circuits |
| A. A. Sakia and E.I. El-Masry | Generation of Equivalent Canonical Digital Filters | |||
| 28th | 1985 | 1986 | G.M Wierzba and J.V. Svobada | A Comparison of Circuits Generated by Op-Amp Relocation |
| 29th | 1986 | 1987 | H. T. Young and K. S. Chao | A High-Resolution Twin-Resistor A/D Conversion Technique |
| 30th | 1987 | 1988 | No winner selected | |
| 31st | 1988 | 1989 | Allen Yi-Jen Chan and C. Y. Roger Chen | A-Algorithm—A New Algorithm for Automatic Test Pattern Generation |
| 32nd | 1989 | 1990 | Moncef Gabbouj and Edward J. Coyle | Design of Stack Filters with Structural Constraints Under the MRE Criterion |
| 33rd | 1990 | 1991 | Hiroyuki Wasaki, Yoshihiko Horio, and Shogo Nakamura | A Localized Learning Rule for Analog VLSI Implementation of Neural Networks |
| 34th | 1991 | 1992 | Russ Duren and Behrouz Peikari | A New Neural Network Architecture for Rotationally Invariant Object Recognition |
| 35th | 1992 | 1993 | Axel Thomsen and Martin M. Brooke | A Temperature Stable Current Reference Source with Programmable Output |
| 36th | 1993 | 1994 | Kaining Wang and Anthony N. Michel | Stability of Dynamical Systems Determined by Differential Inequalities with Applications to Nonlinear Circuits |
| 37th | 1994 | 1995 | Andreas Andreou and Kwabena Boahen | A 48,000 Pixel 580,000 Transistor Silicon Retina in Current-Mode Subthreshold CMOS |
| Shomit M. Ghosh, Wasfy B. Mikhael, and Samuel D. Stearns | Comparative Evaluations of 2-D Predictor Implementations for Lossless Compression of Images | |||
| 38th | 1995 | 1996 | A.G. Dempster and M.D. Macleod | Variation of FIR Filter Complexity with Order |
| 39th | 1996 | 1997 | Mark N. Martin, Philippe O. Pouliquen, Andreas G. Andreou and Martin Fraeman | Current-mode Differential Logic Circuits for Low Power Digital Systems |
| 40th | 1997 | 1998 | Celestino A. Corral, Claude S. Lindquist, and Peter B. Aronhime | Sensitivity of the Band-Edge Selectivity of Various Classical Filters |
| 41st | 1998 | 1999 | E. Alarcón, M. Iannazzo, J. Madrenas, J.M. Moreno, S. Gomáriz, F. Guinjoan and A. Poveda | Implementation of an Application-Specific Fuzzy Controller by Means of a Mixed-Signal Sequential Architecture |
| 42nd | 1999 | 2000 | Samuel L. SanGregory, Charles Brothers, David Gallagher, and Ray E. Siferd | A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation |
| 43rd | 2000 | 2001 | Asad Azam, Dhinesh Sasidaran, Karl Nelson, Gary Ford, Louis Johnson, and Michael Soderstrand | Single-Chip Tunable Heterodyne Notch Filters Implemented in FPGAs |
| 44th | 2001 | 2002 | Henry H. Y. Chan and Zeljko Zilic | Substrate Coupled Noise Reduction and Active Noise Suppression for Mixed-Signal System-on-a-Chip |
| 45th | 2002 | 2003 | Geoffrey A Williamson and Daniel A. Bailey | Channel Equalization Using Adaptive Subband Filters |
| 46th | 2003 | 2004 | Alexandre Marsolais, M. El-Gamal and M. Sawan | A CMOS Frequency Synthesizer Covering the Lower and Upper Band of 5GHz WLANs |
| 47th | 2004 | 2005 | K. M. Tsui, S. C. Chan and K. W. Tse | Design of Complex-Valued Variable Digital Filters and Its Application to the Realization of Arbitrary Sampling Rate Conversion for Complex Signals |
| 48th | 2005 | 2006 | B. Choubey and S. Collins | Low dark current logarithmic pixels |
| 49th | 2006 | 2007 | Ta-chien Huang and Charles Zukowski | Reconfigurable Digital/Analog Processor Array for the Simulation of Gene Regulatory Networks |
| 50th | 2007 | 2008 | José C. Garcia, J. A. Montiel–Nelson, H. Navarro, J. Sosa, and S. Nooshabadi | High Performance CMOS Symmetric Low Swing to High Swing Converter for On–Chip Interconnects |
| 51st | 2008 | 2009 | No winner selected | |
| 52nd | 2009 | 2010 | Niklas Zimmermann, Björn Thorsten Thiel, Renato Negra, and Stefan Heinen | System Architecture of an RF-DAC Based Multi-Standard Transmitter |
| 53rd | 2010 | 2011 | Matthew Turner and John Naber | The Design of a Bi-Directional, RFID-Based ASIC for Interfacing with SPI Bus Peripherals |
| 54th | 2011 | 2012 | Masaaki Fujii | Adaptive and Iterative ITI Canceller for Inter-Track Asynchronous Shingled Write Recording |
| 55th | 2012 | 2013 | Socrates D. Vamvakos, Claude R. Gauthier, Chethan Rao, Karthisha Ramoshan Canagasaby, Prashant Choudhary, Sanjay Dabral, Shaishav Desai, Mahmudul Hassan, K.C. Hsieh, Bendik Kleveland, Gurupada Mandal, Richard Rouse, Ritesh Saraf, Alvin Wang, Jason Yeung, Khaldoon Abugharbieh, and Ying Cao | A 2.488-11.2 Gb/s Multi-Protocol SerDes in 40nm Low-Leakage CMOS for FPGA Applications |
| 56th | 2013 | 2014 | Kushal Das and Torsten Lehmann | Mismatch Insensitive Automatic Tuning Control for the Single Electron Transistor Readout Circuit |
| 57th | 2014 | 2015 | Ho Joon Lee, Yong-Bin Kim and Kyung Ki Kim | Full custom implementation of a S-Box circuit architecture using power gated PLA structure |
| 58th | 2015 | 2016 | Areeb Ali, Neelanjana Pal, and Peter M. Levine | CMOS impedance spectroscopy sensor array with synchronous voltage-to-frequency converters |
| 59th | 2016 | 2017 | Tim Poguntke and Karltheinz Ochs | Linear time-variant system identification using FMCW radar systems |
| 60th | 2017 | 2018 | Hossein Hosseinzadeh, Mihailo Isakov, Mostafa Darabi, Ahmad Patooghy, and Michel A. Kinsy | Janus: An Uncertain Cache Architecture to Cope with Side Channel Attacks |
| 61st | 2018 | 2019 | Yangyang Zhao, Mona E. Zaghloul, and Yigal Lilach | Design and Fabrication of a Plasmonic Gas Sensor |
| 62nd | 2019 | 2020 | Zemin Liu, Yu-Pin Hsu and Mona Mostafa Hella | An Improved OCV-Based MPPT Method Targeting Higher Average Efficiency in Thermal/Solar Energy Harvesters |
| 63rd | 2020 | 2021 | No winner selected | |
| 64th | 2021 | 2022 | No winner selected | |
| 65th | 2022 | 2023 | No winner selected | |
| 66th | 2023 | 2024 | Digvijay Rajurkar, Vidya Sagar Reddy Gopala and Srimathi Govindan | Parasitic Extraction Modeling for Standard Cell Library on Intel 4 Technology |
| 67th | 2024 | 2025 | Abed Benbuk, Diogo Moniz-Garcia, Daniel Gulick, Alfredo Quinones-Hinojosa, and Jennifer Blain Christen | A Miniaturized Wireless, Battery-Free Implant for In Vivo Musculoskeletal Stimulation |
| 68th | 2025 | 2026 | Dong-Hyeon Kim, Kihun Kim, Jun-Seo Kim, Jae-Koo Park, Dae-Won Rho, Jae-Ho Lee, Seung-Jae Yang, and Woo-Young Choi | A 40-Gb/s PAM-4 VCSEL Driver with Reconfigurable 3-Tap Fractionally Spaced FFE |
| 69th | 2026 | 2027 | To be Awarded Next Year |